1. Technical Field
The present invention relates generally to semiconductor integrated circuits (IC) and, more particularly, to a delay locked loop (DLL) circuit in a semiconductor IC.
2. Related Art
A conventional DLL circuit included in a semiconductor IC device is used to supply an internal clock signal having a phase earlier than that of a reference clock signal acquired by converting an external clock signal by a predetermined time. When the internal clock signal utilized in the semiconductor IC is delayed through a clock buffer and a transmission line to have a phase difference from the external clock signal, the DLL circuit is used to solve a resultant problem in that an output data access time is extended. The DLL circuit controls a phase of the internal clock signal to be earlier than that of the external clock signal by a predetermined time in order to increase a valid data output interval.
The conventional DLL circuit includes a clock input buffer, a delay line, a shift register, a clock driver, a replica delayer, a phase detector, and an update control apparatus. The phase detector compares a phase of a reference clock signal output from the clock input buffer with a phase of a feedback clock signal output from the replica delayer. The update control apparatus transmits a phase comparison result of the phase detector to the shift register. As the speed of the device increases, the variation of the phase comparison detection result increases, and an abnormal operation may occur. The update control apparatus is provided to prevent the abnormal operation. The update control apparatus accumulates the phase comparison result values. When the accumulated values reach a predetermined value, the update control apparatus controls a delay value that the shift register supplies to the delay line to be updated.
The conventional update control apparatus is implemented using a low pass filter. That is, when the phase comparison detection value maintains the same values for a predetermined number of cycles, the update control apparatus generates and transmits an update control signal to the shift register. However, such an update control apparatus has a complicated update condition. For example, when the update control apparatus operates in response to three consecutive phase comparison detection result values, the update control apparatus may generate a normal update control signal with respect to values (0, 0, 0) or (1, 1, 1), but cannot generate the update control signal when values of (0, 0, 1) is repeated. Subsequently, the update operation using the update control apparatus is ineffective and the DLL circuit with the above update control apparatus is limited in that the update control apparatus cannot accurately control the phase of the internal clock signal.